Throughput and bottlenecks
Amdahl's lawwhy is it slowcache and network performancescaling limits
Amdahl and Gustafson, cache miss penalty, bandwidth-delay product and transfer time: why a machine never hits its rated speed.
Amdahl's Law (Speedup from Parallelisation)
Speedup of a fixed workload on N processors when a fraction p of it can be parallelised. The serial remainder sets a hard ceiling no amount of hardware can pass.
Gustafson's Law (Scaled Speedup)
Speedup when the problem grows to fill the machine rather than staying fixed: linear in the processor count, with no ceiling. Here p is the parallel share of the run time on the large machine.
Average Memory Access Time (AMAT)
What a memory reference costs on average once cache misses are counted: the hit time every access pays, plus the miss penalty paid on the fraction that miss. Stated in clock cycles.
Bandwidth-Delay Product
How many bits are in flight on a link at any instant: the rate multiplied by the round-trip time. A sender whose window is smaller than this can never fill the pipe, however fast the link is.
File Transfer Time
Time to move a file at a sustained throughput: size divided by rate. Enter the size in megabytes and the rate in megabytes per second, and the answer comes back in seconds.
How they fit together
Every formula in this set exists because a rate on a spec sheet is an average over parts that do not all get faster together. Amdahl's law is the bluntest statement of it: whatever fraction of a program stays serial sets a ceiling on speedup that no hardware budget passes. Code that is 95% parallel cannot exceed 20x however many cores you buy, and the last doubling of the machine typically buys a few percent.
Gustafson's law is the honest rebuttal, and the two are usually presented as rivals when they are really answers to different questions. Amdahl fixes the problem size and asks how much sooner it finishes. Gustafson lets the problem grow to fill the machine and asks how much more gets done in the same wall-clock hour. Supercomputers are bought on Gustafson's premise and benchmarked, unfairly, on Amdahl's. Decide which question you are actually asking before quoting either number.
The last three are the same arithmetic applied to hardware. AMAT shows why a 2% cache miss rate with a 200-cycle penalty gives an average access of five cycles rather than one, so the rare case dominates the common one. Bandwidth-delay product is the network version, and it is the reason a gigabit link across an ocean delivers a trickle to a sender whose window is too small. The pipe is not full, and no amount of bandwidth fixes a window problem. Transfer time is the sanity check at the end, and it is worth running before anyone orders a bigger circuit, because compressing the file first is usually the cheaper fix.