Semiconductors & Chips formulas — 13 solvers

CMOS Dynamic Switching Power

P = \alpha C V^2 f

Semiconductors & ChipsPower a CMOS chip burns charging and discharging its own capacitance: the activity factor, the switched capacitance, the supply voltage squared, and the clock frequency. The squared voltage is the reason every process generation chased a lower rail.

Dennard Scaling and Power Density

\frac{P''_{new}}{P''_{old}} = \left(\frac{\kappa}{\nu}\right)^2

Semiconductors & ChipsHow power per unit of chip area changes when dimensions shrink by κ but supply voltage only shrinks by ν. Dennard's 1974 rules had the two equal, and power density stayed constant. When ν fell behind κ, it stopped.

Die Yield from Defect Density (Poisson Model)

Y = e^{-D_0 A}

Semiconductors & ChipsFraction of dies with no fatal defect, when defects fall randomly on the wafer at a known density. Because the area sits in an exponent, doubling the die size does far worse than halving the yield.

Energy per Switching Event

E = \tfrac{1}{2} C V^2

Semiconductors & ChipsEnergy delivered to a capacitive node each time it is charged to the supply rail. Answers come back in joules because the units engine has no femtojoule — a 1 pF node at 1 V stores 5e-13 J, which is 0.5 pJ.

Gate Propagation Delay from an RC Load

t_p = R C \ln 2

Semiconductors & ChipsTime for a logic gate's output to cross the halfway point when it drives a capacitive load through its own on-resistance. The output is an RC step response, and the 50% crossing sits at exactly one time constant times the natural log of 2.

Gross Dies per Wafer

N = \frac{\pi D^2}{4A} - \frac{\pi D}{\sqrt{2A}}

Semiconductors & ChipsStandard geometric estimate of how many square dies fit on a round wafer. The first term is the wafer area divided by the die area; the second subtracts the ring of partial dies that fall off the curved edge.

Junction Temperature from Power and Thermal Resistance

T_j = T_a + P R_{\theta JA}

Semiconductors & ChipsHow hot the silicon gets: ambient temperature plus the power dissipated multiplied by the thermal resistance from junction to air. It is Ohm's law with temperature for voltage, watts for current, and K/W for ohms.

Maximum Clock Frequency from the Critical Path

f_{max} = \frac{1}{t_{pd} + t_{su}}

Semiconductors & ChipsFastest clock a synchronous design can be run at: the reciprocal of the slowest register-to-register path plus the setup time the receiving flip-flop demands. Everything else in timing closure is a correction to these two terms.

Moore's Law Doubling

N = N_0 \, 2^{t/T}

Semiconductors & ChipsTransistor count on a chip after a stretch of time, doubling on a stated period. Moore's 1965 paper claimed a doubling every year; he revised it to every two in 1975, and the two-year figure is the one that held for four decades.

MOSFET Drain Current in Saturation (Square Law)

I_D = \tfrac{1}{2} k_n \frac{W}{L} (V_{GS} - V_{th})^2

Semiconductors & ChipsDrain current of a MOSFET held above threshold with enough drain voltage to pinch off the channel. The current depends on the square of the overdrive and, to first order, not on the drain voltage at all — which is what makes the device a current source.

MOSFET Drain Current in the Linear (Triode) Region

I_D = k_n \frac{W}{L}\left[(V_{GS} - V_{th})V_{DS} - \frac{V_{DS}^2}{2}\right]

Semiconductors & ChipsDrain current when the drain-source voltage is below the overdrive and the channel reaches all the way across. At small drain voltages the square term vanishes and the transistor is simply a resistor the gate can adjust.

Shockley Diode Equation

I = I_s\left(e^{V/(n V_T)} - 1\right), \quad V_T = \frac{kT}{q}

Semiconductors & ChipsCurrent through a p-n junction as a function of the voltage across it. The thermal voltage kT/q is computed from the temperature you enter — 25.85 mV at 300 K — because the temperature dependence is the whole point of the equation.

Total Chip Power: Dynamic plus Leakage

P_{tot} = \alpha C V^2 f + V I_{leak}

Semiconductors & ChipsWhat a chip actually burns: the switching term plus the current that flows through transistors that are supposed to be off. Below about 65 nm the second term stopped being a rounding error and became a design constraint.