Gross Dies per Wafer

Also known as dies per wafer · gross die count · die per wafer estimate · wafer utilisation · how many chips on a wafer · edge die loss · DPW

N = \frac{\pi D^2}{4A} - \frac{\pi D}{\sqrt{2A}}

dies

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Square dies on a round wafer: the first term of this estimate is simply the wafer's area divided by the die's, and the second subtracts the ring of dies that hang over the curved edge and cannot be used. That second term is a circumference divided by a die edge length, which is why it scales as $D/\sqrt{A}$ rather than as an area, and why it hurts large dies disproportionately.

The formula explains the industry's steady march in wafer size — 100 mm, 150, 200, and 300 mm since around 2001 — better than any other single relation. Area goes as the square of the diameter while edge loss goes only as the first power, so a larger wafer wastes proportionally less. Processing cost per wafer rises far more slowly than the area does, so cost per die falls. The 450 mm transition was planned, tooled up for, and then abandoned around 2013 to 2016 because the equipment cost could not be justified against slowing volume growth, which is a reminder that the economics in these formulas are as binding as the physics.

Treat the number as an estimate rather than a count, because a real fab gets it from a stepper map. The true figure depends on where the reticle grid is placed relative to the wafer centre, on the edge exclusion zone — typically 3 to 5 mm where processing is unreliable and no die is placed — and on the scribe lanes between dies that the saw consumes. Test structures also take space, usually in the scribe lanes. And whatever the arithmetic says, round DOWN: there is no such thing as most of a die.

Multiply this count by the yield from the defect model and you have good dies per wafer, which divided into the wafer's processing cost is the number the whole business runs on. It is worth doing that division once with real figures to feel how the two effects compound: a die twice as large gives you fewer than half as many candidates AND squares the yield on each, so cost per good die can easily quadruple for a doubling of area. That compounding is the reason die size is defended so fiercely in a chip's architecture reviews.

Gross Dies per Wafer

N = \frac{\pi D^2}{4A} - \frac{\pi D}{\sqrt{2A}}

Where

$N$ = Gross dies per wafer (dies)
$D$ = Wafer diameter (mm)
$A$ = Die area (mm²)

Missing one of these? Work it out first, then come back

Gross dies per wafer — Moore's Law Doubling, Recipe Scaling (Ingredient for a New Yield)
Wafer diameter — Area Moment of Inertia — Solid Round Bar, Polar Moment of Inertia — Solid Shaft
Die area — Die Yield from Defect Density (Poisson Model), Area of a Circle