A chip's power and heat budget
CMOS power calculationdynamic and leakage powerjunction temperaturethermal budgetwhy is my chip hot
What a CMOS part costs in watts and degrees: the clock its critical path allows, dynamic and leakage power, and the junction temperature.
Gate Propagation Delay from an RC Load
Time for a logic gate's output to cross the halfway point when it drives a capacitive load through its own on-resistance. The output is an RC step response, and the 50% crossing sits at exactly one time constant times the natural log of 2.
Maximum Clock Frequency from the Critical Path
Fastest clock a synchronous design can be run at: the reciprocal of the slowest register-to-register path plus the setup time the receiving flip-flop demands. Everything else in timing closure is a correction to these two terms.
Energy per Switching Event
Energy delivered to a capacitive node each time it is charged to the supply rail. Answers come back in joules because the units engine has no femtojoule — a 1 pF node at 1 V stores 5e-13 J, which is 0.5 pJ.
CMOS Dynamic Switching Power
Power a CMOS chip burns charging and discharging its own capacitance: the activity factor, the switched capacitance, the supply voltage squared, and the clock frequency. The squared voltage is the reason every process generation chased a lower rail.
Total Chip Power: Dynamic plus Leakage
What a chip actually burns: the switching term plus the current that flows through transistors that are supposed to be off. Below about 65 nm the second term stopped being a rounding error and became a design constraint.
Junction Temperature from Power and Thermal Resistance
How hot the silicon gets: ambient temperature plus the power dissipated multiplied by the thermal resistance from junction to air. It is Ohm's law with temperature for voltage, watts for current, and K/W for ohms.
How they fit together
Run this set in the order a design actually resolves: find the clock the silicon can hold, then find the power that clock costs, then find out whether the package can get rid of it. RC propagation delay is the bottom of the stack. A gate charging a capacitive load through a finite drive resistance is the whole reason digital logic has a speed limit at all, and the two ways to make it faster — a wider transistor for lower R, a shorter or lighter-loaded wire for lower C — are the two levers the rest of the physical design is built around. Maximum clock frequency then adds setup time and inverts the critical path. The number to be careful with is which path: fmax is set by the single slowest path in the design, not the average, so one badly routed net caps the entire part.
Power follows the clock, and the middle three formulas are best read as one idea in three sizes. Energy per switching event is ½CV², the cost of one transition. Dynamic power is that energy multiplied by how often it happens — αCV²f — and the V² in it is the entire reason voltage scaling was worth pursuing so hard: dropping the supply 20% takes 36% off dynamic power, while dropping the clock 20% takes only 20%. The activity factor α is where estimates go astray, because it is rarely near 1. Typical logic switches on maybe 10 to 20% of clock edges, and using α = 1 overstates a chip's power by five times or more.
Total power with leakage is the correction that turned CMOS from a low-power technology into a thermally limited one. Leakage does not care whether the clock is running, so it does not scale away when you idle the part, and below roughly 65 nm it stopped being a rounding error and became a third or more of the budget. That is what put an end to simply lowering the threshold voltage for speed. Junction temperature is the last line and the one that decides whether the fmax you calculated at the top was ever real: Ta + P·Rθja. If it lands over the rated Tj the part will throttle, and it throttles the clock, which sends you back to the first formula. Note the ambient in that equation is the air inside the enclosure and not the room — a 25 °C office is often a 45 °C case interior, which is 20 °C straight off your thermal margin before the heatsink has done anything at all.