Gate Propagation Delay from an RC Load

Model a logic gate crudely and usefully: a switch with an on-resistance $R$, driving a load capacitance $C$ that is the sum of the input capacitances of everything downstream plus the wire between them. Flip the switch and the output follows an exponential toward the rail. The 50% crossing — the conventional definition of propagation delay, because that is where the next gate decides — arrives at $RC\ln 2$, which is $0.69RC$.

Two design levers fall straight out of it. Delay is proportional to load, so a gate driving many inputs is slow, and the fix is a buffer chain: rather than one small gate driving a huge load, insert progressively larger buffers, each with a modest fanout. The optimum ratio between successive stages works out near $e$ in the idealised case and is taken as roughly 3 to 4 in practice, and the whole of logical-effort sizing is an elaboration of that idea. Delay is also inversely proportional to drive, so a transistor twice as wide is twice as fast — but it presents twice the input capacitance to whatever drives it, and that trade is the reason sizing is a global problem rather than a local one.

What the model gets wrong is the transistor. A MOSFET is not a resistor: above threshold and in saturation its current is roughly constant regardless of drain voltage, so the charging is closer to a constant-current ramp than an exponential, and a better first-order delay is $t_p \approx C V / I_{on}$. The $R$ used here is an effective resistance fitted over the voltage swing, not something you can measure with a meter, and it changes with the supply rail. Treat the RC form as the right way to get the scaling relationships in your head, and treat a circuit simulator as the way to get a number you will sign off on.

One more term matters at modern nodes and is invisible in this equation: the wire. Interconnect resistance and capacitance both grew in importance as dimensions shrank, and a long global wire has a delay proportional to the square of its length because both its $R$ and its $C$ rise together. Repeaters — buffers inserted along the wire to break it into shorter segments — restore linearity, and on a large chip the repeaters can consume a serious fraction of both the area and the power budget. Gate delay stopped being the whole story some time ago.