Total Chip Power: Dynamic plus Leakage
Also known as total power CMOS · dynamic plus static power · leakage power · static power · subthreshold leakage power · why idle chips get warm · power wall
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Total chip power has three sources, and the tidy story only covers one. Dynamic switching power, , is the charge moved onto and off the load capacitance. Short-circuit power flows during the few picoseconds when an input is mid-transition and both the pull-up and pull-down transistors are partly conducting, briefly shorting the rail to ground — normally a few percent of the dynamic term, and larger where input edges are slow. Static or leakage power is current flowing through transistors that are nominally off, and it flows whether or not anything is happening.
Leakage is not one mechanism but several. Subthreshold conduction is the dominant one: a MOSFET below its threshold does not stop conducting, it conducts exponentially less, falling by roughly a factor of ten for every 60 to 100 mV the gate drops below threshold. Gate-oxide tunnelling appears once the oxide is only a few atomic layers thick, which is why high- dielectrics were introduced around the 45 nm node. Junction leakage across reverse-biased drain junctions adds a smaller third contribution.
Two consequences follow, and they have reshaped how chips are built. First, clock gating does nothing for leakage — a block with its clock stopped still leaks — so power gating, cutting the supply rail to the block entirely with a header transistor, became the serious tool, at the cost of state loss and a wake-up penalty. Second, leakage roughly doubles for every 10 °C rise, so a hot chip leaks more, which makes it hotter. That feedback loop is real thermal runaway and it is one reason processors throttle aggressively rather than gracefully.
The measurement trap worth knowing: a leakage figure quoted at 25 °C bears little relation to what the part does at an 85 °C junction, and the ratio is not a small correction — six doublings is a factor of sixty. When a power budget is being defended, the leakage number has to be quoted at the worst-case junction temperature the design will actually reach, which is the temperature the thermal calculation returns rather than the one on the bench.
- = Total power (W)
- = Activity factor
- = Switched capacitance (nF)
- = Supply voltage (V)
- = Clock frequency (GHz)
- = Leakage current (A)
- Total power — Power (P = W/t), Power from Force and Velocity (P = Fv)
- Activity factor — CMOS Dynamic Switching Power, Shockley Diode Equation
- Switched capacitance — CMOS Dynamic Switching Power, Energy per Switching Event
- Supply voltage — CMOS Dynamic Switching Power, Energy per Switching Event
- Clock frequency — CMOS Dynamic Switching Power, Maximum Clock Frequency from the Critical Path
- Leakage current — MOSFET Drain Current in Saturation (Square Law), MOSFET Drain Current in the Linear (Triode) Region