CMOS Dynamic Switching Power

A CMOS gate that is not switching draws almost nothing. That is the whole design idea, and it is why CMOS displaced every logic family that came before it. The price is paid on the transitions: every time a node goes from low to high, the supply has to push charge $CV$ onto it, and every time it goes back down that charge is thrown away to ground. Do that $f$ times a second on the fraction $\alpha$ of the chip that is actually toggling, and the bill is $P = \alpha C V^2 f$.

The four terms are not equally useful to a designer. The activity factor is a property of the workload and the architecture, and clock gating — shutting the clock off to blocks that have nothing to do — is the standard way to attack it. Capacitance is set by the process and the layout, and shrinking the transistors shrinks it. Frequency is linear, which sounds attractive until you notice that halving the clock halves the power and halves the work done, so nothing is gained per unit of computation.

The voltage is the term that does not play fair, and it is the reason this equation is worth memorising. It is squared, so a 30% cut in the supply rail halves the power outright. Between about 1990 and 2005 the industry took the supply from 5 V to roughly 1 V, and that alone bought a factor of 25 in power per switching event. Nothing else in the equation ever offered leverage like that, and nothing has since — the rail has been stuck near 1 V for two decades because the transistor stops switching cleanly once the supply approaches its threshold voltage.

The classic error here is quoting this figure as "the chip's power". It is not. It is the dynamic component alone, and on any process below roughly 65 nm the leakage term sitting beside it can be a third of the total, rising steeply with temperature. A power model built from $\alpha C V^2 f$ and nothing else will underpredict a modern part, will underpredict it worst when the part is hot, and will therefore fail exactly when the answer mattered.