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Maximum Clock Frequency from the Critical Path

Also known as max clock speed · critical path frequency · setup time limit · timing closure · how fast can this run · clock period from path delay · fmax

fmax=1tpd+tsuf_{max} = \frac{1}{t_{pd} + t_{su}}

Enter your known values, leave one input blank, and solves for the missing one. Try different units for next level excitement!

See also
Gate Propagation Delay from an RC Load — The gate delays that add up to the critical path in the first place.CMOS Dynamic Switching Power — Every hertz won here is paid for in switching power, linearly.Amdahl's Law (Speedup from Parallelisation) — When frequency stopped rising, cores were added instead — and this is the ceiling on what that bought.

Learning zone

A synchronous design works if, in every clock period, data launched from one flip-flop arrives at the next one and is stable before that flip-flop samples. The period therefore has to cover the whole journey: the clock-to-Q delay of the launching flip-flop, the combinational logic between them, and the setup time the receiving flip-flop demands before its own clock edge. The reciprocal of that sum is the fastest the design can be clocked, and the slowest such path on the chip is the critical path.

Timing closure — the process of making every path meet its period — is most of the back-end work on a digital design, and it has a vocabulary worth knowing. Slack is the margin by which a path passes or fails; negative slack is a violation. Clock skew is the difference in arrival time of the clock edge at the two flip-flops, and it is not simply harmful: skew in the direction of data flow lends time to a slow path, and deliberate useful skew is a real optimisation. Jitter, the cycle-to-cycle wobble of the clock source, always subtracts, because the design has to work on the worst cycle rather than the average one.

The other constraint gets forgotten, and it fails silently. Setup time says data must not arrive too LATE; hold time says it must not arrive too EARLY, changing the receiving flip-flop's input before that flip-flop has captured the previous value. A setup violation can be fixed by slowing the clock down. A hold violation cannot be fixed by any clock frequency at all, because it does not depend on the period — it is a race between the data path and the clock path, and the fix is to add delay to the data. A part with a hold violation is broken at every speed, which is why hold checking happens even on designs with acres of setup margin.

Historically this equation is where the frequency race lived, and where it died. Clock speeds climbed from megahertz to nearly 4 GHz over about twenty years by shortening the critical path — deeper pipelines with less logic per stage, faster transistors, better circuit styles. It stopped around 2005, and not because the paths could not be shortened further: it stopped because P=αCV2fP = \alpha C V^2 f is linear in frequency while the voltage needed to reach that frequency had stopped falling. The industry left the clock where it was and started adding cores, at which point the ceiling on the benefit moved from this equation to Amdahl's law.

Maximum Clock Frequency from the Critical Path
fmax=1tpd+tsuf_{max} = \frac{1}{t_{pd} + t_{su}}
tpdtsuf
Where
  • fmaxf_{max}= Maximum clock frequency (GHz)
  • tpdt_{pd}= Critical path delay (s)
  • tsut_{su}= Setup time (s)
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